1. Field of the Invention
The present invention relates to testing of computer integrated circuits ("chips"). More particularly, the present invention relates to an apparatus for reducing the cost and improving the efficiency of testing computer chips and their associated system, in the computer chips normal operating environment.
2. History of the Prior Art
The efficient design and implementation of complex computer chips in increasingly sophisticated computer systems often requires that the computer chips be tested as they operate in conjunction with the other computer chips which comprise the system. Accurate off-board testing of many computer chips is very difficult because testing a chip independently from its overall system invariably ignores a vast array of test signal combinations that the chip will encounter during actual operation on the host board. Moreover, each chip must remain mounted on the host board if operation of the entire system is to be properly analyzed.
Systems designers long ago recognized the inefficiencies and inevitable pitfalls associated with off-board testing of computer chips. As a result, designers began testing computer chips and complete systems operation as the computer chips functioned in their normal operating environment with the computer chips mounted on the host board. This testing method, however, has a number of inherent problems and disadvantages.
These inherent problems and disadvantages arose primarily because the pins on a chip are not easily accessible to test equipment when the chip is mounted on a host board. Prior attempts at accessing the pins on a computer chip as it operates on a host board have been accomplished in a variety of ways. The most popular approach to testing a chip as it operates in conjunction with other chips on a host board has been to physically turn the entire host board on its side and then use a probe to contact the underside connections of the pins on the chip. By doing so, the designer can use an oscilloscope to view the signals appearing on the tested pin.
The first problem with testing chips with a probe is that one must inconveniently tilt the entire board upward in order to see the underside pin connections. Once the board has been tilted, the top of the chip is no longer visible, i.e. one cannot see both sides of the chip at the same time. Since pin labeling schemes typically only label the pins with reference to a top view of the chip, it is difficult for the designer to identify one pin from the next when only viewing the underside of the chip. This predicament forces the designer to constantly tilt the board back and forth in order to coordinate the pin arrangement from the top of the chip with its arrangement from the bottom to be sure he is placing the probe on the correct underside pin connection. This testing method becomes increasingly difficult as the number of pins on the tested chip increases. For example, it is not uncommon for some computer chips to have over one hundred pins. Realistically, whenever a chip has more than about ten pins, it becomes difficult for the designer to keep track of all of the pins because they are all spaced very close together and there can be many different pins performing an equally large number of different functions. Moreover, many multi-pinned chips create an additional problem for the designer because all of the pins accessible from the underside of the board may not be visible from the top side of the chip. The ceramic package of the chip itself often hides a number of pins positioned directly under it. Hence, the designer must try to compare the top view of a pin diagram with the underside pin configuration of the chip as it sits in the host board, a confusing and timely chore to say the least.
A second chip testing problem arises when the designer is forced to turn the host board on its side in order to access the electrical connections to the pins on a chip. The described requirement of constantly tilting the host board back and forth creates harmful stress on the board itself. Stress weakens the board and the metal traces that form the electrical connections between the pins on all of the chips mounted on the host board. Too much stress on the board can cause the trace connections to break. A broken trace connection creates an open circuit between two pins and, consequently, renders the entire board useless. Thus, not only does tilting the board result in inefficient, cumbersome testing, but it can also result in the costly requirement of replacing the entire host board and further delay testing of the chip and the system.
Systems designers who test computer systems and the computer chips which comprise those systems also encounter testing problems associated with the probe that is used to sense signal levels on the pin of a board-mounted computer chip. These problems principally include the occurrence of unpredictable damaging arcs of electrical charge which emanates from the probe and falls on nearby trace connection lines. An arc from the probe to a trace connection line can cause the trace to burn out. A burnt out trace line results in a break in the electrical connection that it forms between pins mounted in the host board. Arcs commonly occur when a probe is used to test a high voltage signal on a pin. As the testing needle of the probe moves too close to one of the trace lines carrying a low voltage signal, the high voltage charge on the probe can arc over to the trace line and cause the trace to melt, thereby breaking the trace connection. Not unlike stress damage, arc damage to traces on the host board can also render the host board useless. Again, not only does this require the costly replacement of the host board, but it further delays the testing of the computer chips and the associated computer system.